Fabrication of 5-7 nm wide etched lines in silicon using 100 keV electron-beam lithography and polymethylmethacrylate resist October 21, 2020 Electron Beam Lithography, Photomask / Direct Write Lithography 0 The present limit of around 10 nm for the width of lines fabricated by e-beam lithography using polymethylmethacrylate (PMMA) resist on silicon substrates has been overcome. 5–7 nm wide etched lines in bulk Si substrates have been produced. A 65 nm thick layer of PMMA was exposed with an 80 kV electron beam of diameter smaller than 5 nm. After exposure the resist was developed in 3:7 cellosolve:methanol with ultrasonic agitation. The pattern in resist was transferred to the Si substrate with reactive ion etching. Lines of width varying between 5 and 7 nm were recorded using an S-900 scanning electron microscope which has a resolution of 0.7 nm. For full details: Attached files often contain the full content of the item you are viewing. Be sure and view any attachments. resources_se/Nanotech-33.pdf 273.1 KB Related Articles Calixarene Electron Beam Resist for Nan0-Lithography New electron beam (EB) resists made of calixarene resists are introduced. Typical sensitivities of calixarene resists range from 700 µC/cm2 to 7 mC/cm2. High-density dot arrays with 15 µm diameter constructed using calixarene resist were easily delineated using a point EB lithography system. Our results suggest that the resolution limit of calixarene resists is dominated by a development process such as adhesion to a substrate rather than by the EB profile. Calixarene resists are resistant to etching by halide plasma. We also demonstrated nanoscale devices processed by using calixarene resists. Calixarene resists are promising materials for nanofabrication. Lithography for sub-60 nm resist nanostructures As the semiconductor community continues to follow the Semiconductor Industry Association Roadmap, resist structures are being printed further into the nanometer domain. However, a persistent issue for successful sub-60 nm resist patterning is mechanical stability at high aspect ratios. The objective of this article is to understand what processing conditions facilitate processing resist nanostructures with useful aspect ratios for the fabrication of sub-60 nm transistors. We have found that, in aqueous based development and rinse, if the resist thickness is reduced, then the aspect ratio is sacrificed for the sake of resolution. The implication is that there is a resolution limit at which resist structures will have aspect ratios that are useful for device fabrication. We have also found that there are development effects that occur in the thick film regime that are not reproducible with thin films. The best resolution structures we have been able to print are lines of 28 nm in width using direct write electron-beam lithography on negative chemically amplified resists NEB-22 and NEB-31 (Sumitomo Chemical Inc.) with an aspect ratio of about 3. To put this result in perspective, this is about 40 molecules wide. High-Resolution Electron-Beam Lithography and Its Application to MOS Devices A point electron-beam lithography system using a thermal field emitter (TFE) allows us to use a nanometer-level fine electron beam to investigate nano-fabrication techniques and minute devices. We developed an organic negative resist, called calixarene, which has low molecular weight of 972 and almost monodispersity. This resist shows a high resolution of about 10 nm when it is exposed to an electron-beam system of 50 kV using TFE. The newly developed resist has been applied in order to fabricate an EJ-MOSFET (electrically variable shallow junction metal-oxide-semiconductor field effect transistor). A 14-nm-gate-length EJ-MOSFET was fabricated by using a calixarene resist and an electron-beam exposure system, and showed MOS device performance. Intra-Level Mix-and-Match Lithography Process for Fabricating Sub-100-nm Complementary Metal-Oxide-Semiconductor Devices using the JBX-9300FS Point-Electron-Beam System To increase the throughput of electron beam lithography used to fabricate sub- 100-nm patterns, we developed an electron beam and deep UV intra-level mix-and-match lithography process, that uses the JBX-9300FS point-electron-beam system and a conventional KrF stepper. Pattern data preparation was improved for sub- 100-nm patterns. To reduce the effect of line width variation caused by post-exposure delay on complementary metal-oxide-semiconductor (CMOS) devices, we first exposed KrF patterns and then added another post-exposure bake before the electron beam (EB) exposure. We have used this technique to expose the gate layer of sub- 100-nm CMOS devices. When we set the threshold size between EB and KrF patterns at 0.16 µm, the throughput of electron beam lithography was about threefold that of the full exposure by the electron beam lithography process. Sub-50-nm CMOS devices with high drive current were successfully fabricated. Fabrication of 30 nm gate length electrically variable shallow-junction metal–oxide–semiconductor field-effect transistors using a calixarene resist We have fabricated electrically variable shallow-junction metal–oxide–semiconductor field-effect transistors (EJ-MOSFETs) with an ultrafine gate for the first time. The gate length was reduced to 32 nm by using electron-beam lithography with a calixarene resist, which has an under 10 nm resolution with a sharp pattern edge. Moreover, normal transistor operation of 32 nm gate-length EJ-MOSFETs was confirmed. Lithographic Performance and Mix-and-Match Lithography using 100 kV Electron Beam System JBX-9300FS We evaluated the performance of 100-kV point electron-beam lithography system: JBX-9300FS and developed Mix-and-Match lithography process. Resolution on resist exposure is 30-nm using commercially available chemically amplified resist and is down to 10-nm-order using Calixarene resist. For high-throughput lithography, Mix-and-Match lithography process was developed including pattern preparation, and EB exposure time decreased to 1/3. These process technologies are useful for development of advanced CMOS devices. Showing 0 Comment Comments are closed.