Single-mode Semiconductor Reference Oscillator Development for Coherent Detection Optical Remote Sensing Applications October 22, 2020 Electron Beam Lithography, Photomask / Direct Write Lithography 0 High power single mode, tunable, narrow linewidth semiconductor lasers in the 2.05-μm wavelength region are needed for coherent detection optical remote sensing applications. 2.05-μm Fabry Perot (FP) and distributed feedback (DFB) ridge waveguide lasers fabricated from epitaxially grown InGaAsSb/AlGaAsSb/GaSb and InGaAs/InP hetero-structures are reported. This work is part of a NASA Earth Science Enterprise Advanced Technology Initiatives Program research effort to develop semiconductor laser reference oscillators for optical remote sensing from Earth orbit. In particular, local oscillators provide the frequency reference required for active spaceborne optical remote sensing concepts that use heterodyne (coherent) detection. The two most prominent Earth observation applications for this technology are Doppler LIDAR wind sensing and tropospheric carbon dioxide measurement by laser absorption spectrometry, the currently favored operational wavelength for both of which is 2.05 μm. For full details: Attached files often contain the full content of the item you are viewing. Be sure and view any attachments. resources_se/Optical-24.pdf 294.66 KB Related Articles Progress toward a 30 nm silicon metal-oxide-semiconductor gate technology We report on progress toward scaling both N-metal–oxide–semiconductor (MOS) and P-metal–oxide–semiconductor MOS transistors to a gate length of 30 nm. We describe lithography and pattern transfer results that are suitable to meet this goal. Scanning capacitance microscopy is used to determine the effective channel lengths and source drain junction depths on cross-sectioned devices to optimize the fabrication process. We present interim electrical results obtained for high performance, down to Lg = 57 nm, N-MOS and P-MOS transistors made during this process. We have also used a device simulation program to predict subthreshold current for N-MOS transistors with gate lengths from 40 to 26 nm. The simulation provides insights into the effects of critical dimension control and edge roughness on leakage current, and has implications for extending large scale integration of MOS technology beyond 50 nm. 50-nm Gate-length InP-based HEMTs for Millimeter-wave Applications InP-based HEMT technology presents substantial performance advantages for millimeter wave applications such as high-speed wireless communications, radio astronomy, and radar. We report on the development of a 50-nm gate-length process for millimeter wave InP HEMTs. The gate patterns were defined using a single electron beam exposure and a bi-layer resist system. The process was evaluated on pseudomorphic InAlAs/InGaAs/InP HEMT material. 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Confinement of domains within the patch boundaries during thermomagnetic recording has also been demonstrated. We have measured polarization conversion of the incident light on the sidewalls of the patches; a method to reduce the amount of such polarization conversion is proposed in this article. Intra-Level Mix-and-Match Lithography Process for Fabricating Sub-100-nm Complementary Metal-Oxide-Semiconductor Devices using the JBX-9300FS Point-Electron-Beam System To increase the throughput of electron beam lithography used to fabricate sub- 100-nm patterns, we developed an electron beam and deep UV intra-level mix-and-match lithography process, that uses the JBX-9300FS point-electron-beam system and a conventional KrF stepper. Pattern data preparation was improved for sub- 100-nm patterns. To reduce the effect of line width variation caused by post-exposure delay on complementary metal-oxide-semiconductor (CMOS) devices, we first exposed KrF patterns and then added another post-exposure bake before the electron beam (EB) exposure. We have used this technique to expose the gate layer of sub- 100-nm CMOS devices. When we set the threshold size between EB and KrF patterns at 0.16 µm, the throughput of electron beam lithography was about threefold that of the full exposure by the electron beam lithography process. Sub-50-nm CMOS devices with high drive current were successfully fabricated. Gate technology for 70 nm metal–oxide–semiconductor field-effect transistors with ultrathin (<2 nm) oxides Results are described for a gate level technology module developed to produce metal–oxide–semiconductor transistors with physical gate lengths of 70 nm and below. Lithography is performed by direct write e-beam lithography (EBL) using a thermal field-emission EBL system in SAL 601 resist. Critical dimension (CD) control, as measured by several methods, is found to depend not only on dose control but also on writing parameters such as pixel spacing. The pattern transfer using a silicon dioxide hard mask is shown to exhibit a trade-off between anisotropy and selectivity. Transmission electron microscopy cross sections reveal that two atomic layers are removed even when the gate oxide stopping layer is completely intact. We report results for gate lengths down to 60 nm with edge roughness on the order of 5 nm, within the acceptable limits for threshold requirements, while stopping the etch process on oxides as thin as 1.2 nm. Showing 0 Comment Comments are closed.