Photomask / Direct Write Lithography Documents

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Intra-Level Mix-and-Match Lithography Process for Fabricating Sub-100-nm Complementary Metal-Oxide-Semiconductor Devices using the JBX-9300FS Point-Electron-Beam System

To increase the throughput of electron beam lithography used to fabricate sub- 100-nm patterns, we developed an electron beam and deep UV intra-level mix-and-match lithography process, that uses the JBX-9300FS point-electron-beam system and a conventional KrF stepper. Pattern data preparation was improved for sub- 100-nm patterns. To reduce the effect of line width variation caused by post-exposure delay on complementary metal-oxide-semiconductor (CMOS) devices, we first exposed KrF patterns and then added another post-exposure bake before the electron beam (EB) exposure. We have used this technique to expose the gate layer of sub- 100-nm CMOS devices. When we set the threshold size between EB and KrF patterns at 0.16 µm, the throughput of electron beam lithography was about threefold that of the full exposure by the electron beam lithography process. Sub-50-nm CMOS devices with high drive current were successfully fabricated.

Lithographic Performance and Mix-and-Match Lithography using 100 kV Electron Beam System JBX-9300FS

We evaluated the performance of 100-kV point electron-beam lithography system: JBX-9300FS and developed Mix-and-Match lithography process. Resolution on resist exposure is 30-nm using commercially available chemically amplified resist and is down to 10-nm-order using Calixarene resist. For high-throughput lithography, Mix-and-Match lithography process was developed including pattern preparation, and EB exposure time decreased to 1/3. These process technologies are useful for development of advanced CMOS devices.

High-Resolution Electron-Beam Lithography and Its Application to MOS Devices

A point electron-beam lithography system using a thermal field emitter (TFE) allows us to use a nanometer-level fine electron beam to investigate nano-fabrication techniques and minute devices. We developed an organic negative resist, called calixarene, which has low molecular weight of 972 and almost monodispersity. This resist shows a high resolution of about 10 nm when it is exposed to an electron-beam system of 50 kV using TFE. The newly developed resist has been applied in order to fabricate an EJ-MOSFET (electrically variable shallow junction metal-oxide-semiconductor field effect transistor). A 14-nm-gate-length EJ-MOSFET was fabricated by using a calixarene resist and an electron-beam exposure system, and showed MOS device performance.

Ten-Nanometer Resolution Nanolithography using Newly Developed 50-kV Electron Beam Direct Writing System

A high energy 50-kV electron beam direct writing system which has a gas introduction line has been developed. Several aspects of the performance of this system are demonstrated. The electron beam size has been improved to be less than 5 nm. 10-nm width line patterns with 50-nm periods in PMMA resist on a thick Si substrate are demonstrated. It is observed that fewer proximity effects occur when a high-energy electron beam is used. 20-nm-width lines and 20-nm-diameter Au•Pd metal patterns have been fabricated by a lift-off method. 14-nm-diameter carbon dot patterns were deposited on a Si substrate by electron-beam-induced deposition using Styrene gas.

Cu Single Damascene Interconnects with Plasma-polymerized Organic Polymers (k=2.6) for High-speed, 0.1µm CMOS devices

For high-speed CMOS devices, triple-layered Cu single damascene interconnects (SDI) with Cu-via plugs are fabricated in hybrid dielectric films of plasma-polymerized divinylsiloxan benzocyclobuten film (p-BCB: k=2.6) and p-CVD SiO2. No degradation of 0.1µm MOSFETs is observed after the full interconnect integration through MOCVD-Cu filling and pad-scanning, local-CMP for Cu polish. The stacked Cu-pads in the high modulus p-BCB film (19Gpa) withstand sever mechanical impact during Al wire bonding. The 0.08µm CMOS transmitter, which consists of 32:8 pre-multiplexer (MUX), 8B10B encoder, 10:1 MUX and DATA driver, is obtained successfully to generate high-speed serial signals up to 6Gb/s. This fabrication process is a key to obtain the high speed CMOS devices with low-k/Cu interconnects.

45-nm Gate Length CMOS Technology and Beyond using Steep Halo

45-nm CMOS devices with a steep halo using a high-ramp-rate spike annealing (HRR-SA) are demonstrated with drive currents of 697 and 292 µA/µm for an off current less than 10 nA/µm at 1.2 V. For an off current less than 300 nA/µm, 33-nm pMOSFETs have a high drive current of 403 µA/µm at 1.2 V. In order to fabricate a steeper halo than these MOSFETs, a source/drain extension (SDE) activation using the HRR-SA process was performed after a deep source/drain (S/D) formation. By using this sequence defined as a reverse-order S/D formation, 24-nm nMOSFETs are achieved with a high drive current of 796 µA/µm for an off current less than 300 nA/µm at 1.2 V.

Evaluation of a 100 kV TFE Electron Beam Nanolithography System

We report on the results of a series of performance evaluation tests of a JEOL model JBX-9300FS electron beam nanolithography system - a next generation spot beam lithography tool. The electron optics feature a high brightness thermal field emission cathode, 100 kV accelerating voltage, and a two stage deflector which is currently operating at a 25MHz deflection rate. The system is the first to use a high precision 20 bit DAC to achieve 1 nm addressability over a 500 µm writing field. The stage has a 255 x 235 mm range of motion in X and Y, respectively and is configured to load 300mm wafers. The stage is positioned with a laser interferometer with a resolution of 0.6 nm.

Progress toward a 30 nm silicon metal-oxide-semiconductor gate technology

We report on progress toward scaling both N-metal–oxide–semiconductor (MOS) and P-metal–oxide–semiconductor MOS transistors to a gate length of 30 nm. We describe lithography and pattern transfer results that are suitable to meet this goal. Scanning capacitance microscopy is used to determine the effective channel lengths and source drain junction depths on cross-sectioned devices to optimize the fabrication process. We present interim electrical results obtained for high performance, down to Lg = 57 nm, N-MOS and P-MOS transistors made during this process. We have also used a device simulation program to predict subthreshold current for N-MOS transistors with gate lengths from 40 to 26 nm. The simulation provides insights into the effects of critical dimension control and edge roughness on leakage current, and has implications for extending large scale integration of MOS technology beyond 50 nm.

High-purity, ultrahigh-resolution calixarene electron-beam negative resist

Calixarene is a promising high-resolution negative electron-beam resist having a resolution of the order of 10 nm because of its low molecular weight. We have made a purified calixarene resist containing metal contaminants whose concentrations are measured in parts per billion and which therefore do not degrade the performance of silicon-based electron devices. The purity of the calixarene itself was also improved and we obtained high-purity calix[6]arene and high-purity calix[7]arene, both of which contain the main component, which is more than 95% of all the calixarene present. The resolution of both purified calixarene resists is almost the same as that of the unpurified calixarene, but the sensitivity of calix[7]arene is higher than that of calix[6]arene because its molecular weight is higher.