What is a FinFET and How Does it Work?
For decades, the planar MOSFET was the bedrock of integrated circuits. But as semiconductor nodes shrank, the physical limits of this 2D design began to show. Engineers faced a critical challenge: "short-channel effects." As the distance between the source and drain decreased, the gate lost electrostatic control, leading to current leakage and increased power consumption.
The industry needed a new transistor geometry. The solution was to go 3D.
Enter the FinFET. This multi-gate transistor architecture revolutionized semiconductor design by enabling the development of advanced nodes. Instead of a planar channel, the FinFET uses a vertical silicon "fin" that rises from the substrate. The gate is wrapped around this fin on three sides, providing superior electrostatic control and mitigating the short-channel effects that plagued its planar predecessors.
This "multi-gate" approach is a key concept. A multi-gate device, as the name implies, has more than one gate on a single transistor. This family of devices includes not only FinFETs but also future architectures like Gate-All-Around (GAA) FETs, which promise even greater control and scaling.
A Quick Primer: Planar vs. FinFET
To understand the difference, imagine a simple cross-section:
- Planar MOSFET: A flat, 2D channel lies on the silicon substrate. The gate sits on top, controlling the flow of current.
- FinFET: A 3D fin of silicon rises vertically. The gate wraps around the fin, creating a larger, more effective control area.
Key terms to know for FinFETs include:
- Fin Height (Hfin): The height of the silicon fin.
- Fin Width (Wfin): The thickness of the fin.
- Pitch: The distance between adjacent fins.
- Gate Length: The length of the gate as it wraps around the fin.
How a FinFET Actually Operates
The genius of the FinFET lies in its 3D gate control. By wrapping the gate around the fin, the FinFET achieves:
- Superior Depletion: The gate can more effectively deplete the channel of charge carriers, leading to a much lower "off-state" leakage current.
- Steeper Subthreshold Slope: The subthreshold slope is a measure of how quickly a transistor can switch from "off" to "on." A steeper slope means a more efficient switch, and FinFETs excel in this regard. This translates to lower power consumption.
- Increased Drive Current: At the same supply voltage (Vdd), a FinFET can deliver a higher drive current than a planar device. This means faster, more powerful processors.
- Parasitics to Watch: The 3D structure also introduces new parasitic capacitances and resistances that must be carefully managed during design and characterization.
Boxed Math: The Fin Aspect Ratio
The electrostatic control of a FinFET is directly related to its fin aspect ratio (Hfin/Wfin). A taller, thinner fin (a higher aspect ratio) provides better gate control and reduces short-channel effects. However, it also presents significant manufacturing and characterization challenges.
Complementary FET (CFET) architectures represent the next step beyond FINFET-based scaling. In a CFET, the n-type and p-type transistors that form a completely metal-oxide semiconductor (CMOS) pair are vertically stacked rather than placed side by side. This vertical arrangement significantly reduces standard cell area without relying on further lateral pitch scaling. CFETs build directly on the gate-control concepts established by “Gate-All-Around” devices, but shift the primary scaling benefit toward stacking and layout efficiency, making them a leading candidate for technology nodes below 2 nm.
Why 3D Geometry Demands New Characterization
The complex, three-dimensional nature of FinFETs presents new challenges for process control and failure analysis. Simply put, you can't characterize what you can't see. Key challenges include:
- Targeting Specific Fins: In dense arrays of fins, isolating a single, specific fin for analysis is a major hurdle.
- Preserving Interfaces: The interfaces between the high-k dielectric and the metal gate (HKMG) stack are critical to device performance. Preparing a sample for analysis without damaging these delicate layers is essential.
This is where JEOL's purpose-built workflows come in.
The JEOL Workflow: From Specimen to Atomic-Scale Analysis
JEOL provides an end-to-end solution for FinFET characterization, from specimen preparation to atomic-scale imaging and analysis.
- Site-Specific Preparation:
- FIB-SEM: Our Focused Ion Beam (FIB) and Scanning Electron Microscope (SEM) systems allow for precise, site-specific milling to isolate the fin of interest.
- Cross Section Polisher™ (CP): For wide, clean, and damage-free cross sections, our CP tools use a broad argon ion beam to gently polish the sample surface. For sensitive materials, our air-isolation options protect the sample from atmospheric contamination.
- High-Resolution Imaging and Analysis:
- JSM-IT800/IT810 FE-SEM: These Field Emission SEMs provide ultra-high-resolution imaging for critical dimension (CD) measurements, line-edge roughness analysis, and defect localization. Integrated Energy Dispersive X-ray Spectroscopy (EDS) provides elemental composition information.
- Atomic-Scale Structure and Chemistry:
- JEM-ARM300F (GRAND ARM): This aberration-corrected STEM (Scanning Transmission Electron Microscope) achieves resolutions of 58-63 pm, allowing for the direct imaging of atomic structures. With integrated EDS and Electron Energy Loss Spectroscopy (EELS), you can perform detailed chemical analysis of the gate stack and interfaces.
- 3D Device Tomography:
- JEOL's STEM/EDS tomography capabilities enable the 3D reconstruction of fins and contacts, providing a complete picture of the device's structure.
Application Example: Creating a TEM Specimen of a FinFET
A typical JEOL workflow for creating a TEM specimen of a FinFET might look like this:
- SEM Targeting: Use a JEOL SEM to locate the specific fin or feature of interest.
- CP or FIB Preparation: Use our Cross Section Polisher™ for a wide, damage-free cross-section, or a FIB-SEM for site-specific milling and lift-out.
- Lift-Out and Mounting: The prepared lamella is carefully lifted out and attached to a grid mounted on a double-tilted TEM holder.
- HR-STEM Imaging and EELS: The specimen is then transferred to a JEM-ARM300F for high-resolution STEM imaging and EELS mapping of the gate oxide and work-function metals.
Common Pitfalls and How JEOL Mitigates Them
- Curtaining and Mechanical Damage: Traditional cross-sectioning methods can introduce artifacts like "curtaining" (vertical lines on the cross-section) and mechanical damage. JEOL's Cross Section Polisher™ (CP) minimizes these effects.
- Beam Damage and Contamination: Sensitive materials can be damaged by the electron beam or contaminated by exposure to air. JEOL's air-isolation transfer systems and advanced beam control technologies protect your sample throughout the workflow.
The Takeaway
The performance and reliability of FinFET devices are inseparable from their atomic-scale structure and chemistry. JEOL's comprehensive, end-to-end workflow—from specimen preparation to imaging and analysis—provides the critical insights needed to shorten development cycles and accelerate process learning.
Discuss a
FinFET specimen-to-analysis workflow on your device—schedule a session with JEOL applications.